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Area and Delay Efficient Digital Comparator
P. Murugeswari and R. Rampriya
Quantum-dot cellular automata (QCA) tend to be an attractive emerging technology suitable for the development of ultra dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. The proposed work uses novel implementation strategies, methodologies and new formulations of basic logic equations to make the comparison function applied to comparator efficient. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. The comparators proposed here exhibit significantly higher speed and reduced overall area. The existing and proposed comparators are synthesized using Xilinx and performance is evaluated in terms of number of gates and delay.
Keywords: Binary comparators, majority gates, Quantum-dot cellular automata (QCA).
Quantum-dot cellular automata (QCA) technology provides a promising opportunity to overcome the approaching limits of conventional CMOS technology – . For this reason, in recent years the design of logic circuits based on QCA received a great deal of attention, and special efforts have been directed towards arithmetic circuits, such as adders –,multipliers – and comparators –.Even though comparators are key elements for a wide range of applications .QCA implementations existing in the literature are mainly provided for comparing two single bits. Only few examples of comparators able to process n-bit operands, with n > 2, are available .The comparator described in  simply computes the XNOR function to check whether two input bits a and b match each other. The structures proposed in – have higher computational capabilities, and circuits able to recognize all the three possible conditions in which a = b, a > b and a< b (full comparators) are described in and . The 1-bit implementation is proposed in  and then improved in , has been exploited in  to design a parallel n-bit full comparator. An example of serial structures is provided in , whereas the n-bit comparator described in  can recognize only the case in which, A and B being the n bit inputs, A = B.