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PTMAC BASED ON RAZOR FOR ENERGY REDUCTION IN DSPKarthika M., Marutharaj T., and Athilingam R.Abstract The power optimization is achievable by dynamic voltage scaling using the fault tolerant technique by improving the accuracy and/or timing performance against power. Energy improvements have a strong dependency on the delay distribution of the circuit and the characteristics of the input signal. The fault tolerant technique is implemented using Razor approach. The target power is also obtained by using the programmable truncated multiplier (PTMAC) at the expense of degradation of the output signal to noise ratio. In the DSP architecture, the combination of PTMAC and fault tolerant technique is used to reduce the supply voltage below the critical level. Truncated multiplication timing modulation properties are analysed and demonstrated using Xilinx 12.1. Finally the two techniques upgrade the energy saving beyond that expected in the DSP architecture. Keywords: Introduction Less power, area with high speed is the main theme in the VLSI based circuit design. Several techniques exist to reduce the energy consumption. Voltage scaling is an effective technique to reduce the energy consumption in CMOS integrated circuits. The (DSP) digital signal processing system may possibly leverage unconventional voltage overscaling (VOS) to reduce energy consumption while maintaining satisfactory signal processing performance. Scaling the supply voltage by a factor of K results in reduction in the dominating dynamic power consumption by a factor of K2 and yields static power benefits [1]. Karthika M.
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