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Back Issues of Engineering & Technology in India - From February 2016
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M. S. Thirumalai
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Triple Adjacent Error Correction (TAEC) Code for Data Bits in Memory Chips
Ayyappan S., M.E.
Srividhya B., M.E. Student
Abstract
In this paper, a new double-adjacent-error- correction and triple -adjacent-error -correction (DAEC- TAEC) code is proposed for simultaneous testing of the most general memory fault models in data bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads and also reduces the complexity. In order to test data bit and check bit arrays simultaneously, the pro-posed DAEC-TAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed DAEC-TAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases in the time required for memory array tests for 16, 32, and 64 data bits per word.
Keywords: Error correction code, fault model, memory test, word-oriented memory.
I. INTRODUCTION
Transient errors are caused by cosmic neutrons, alpha particles, and radiations and have emerged as a key reliability concern in semiconductor memories .Error correction code (ECC) techniques have been widely used to correct transient errors and improve the reliability of memories. ECC words in memories consist of data bits and additional check bits because the ECCs used in memories are typically from a class of linear block codes. During the write operations of memories, data bits are written in data bit arrays, and check bits are concurrently produced using the data bits and stored in check bit arrays. The check bit arrays, just like the data bit arrays, should be tested prudently for the same fault models if reliable error correction is to be insured. However, it is not feasible to directly access check bit arrays from outside the chip, and additional test time and hardware overheads are often unavoidable for check bit screening [4], [5]. Also, memory test cost increases due to the additional test time for the check bit array and hardware overheads.
This is only the beginning part of the article. PLEASE CLICK HERE TO READ THE ENTIRE ARTICLE IN PRINTER-FRIENDLY VERSION.
Ayyappan S.
Assistant Professor
ayps23@gmail.com
Srividhya B., M.E. Student
srivalar92@gmail.com
Department of Electronics & Communication Engineering
Sri Subramanya College of Engineering & Technology
NH - 209, Sukkamanaickenpatti
Palani 624615
Tamil Nadu
India
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